I’ve been working on a Reaktor project that required a modified modulo, so I built some modulo core cells based off the IMod Core Macro. I made them both Core Cells and Core Macros. Also, the Divisor is prevented from being <= 0, and the output order of the module is Div, then Mod. I did [...]
Monthly Archives: July 2012
It seems that in using my arduinome today, that Reaktor really preferes to work with ports higher then the 8000/8080. I ended up using 10000/10001, and the messages became much more consistent. If you’re running into issues with Reaktor and OSC, this might be worth a shot.